diff -Naur u-boot-1.1.3/board/actelm7/actelm7.c u-boot-actelm7/board/actelm7/actelm7.c
--- u-boot-1.1.3/board/actelm7/actelm7.c	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/board/actelm7/actelm7.c	2009-09-06 00:40:18.000000000 +0100
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <command.h>
+
+#ifdef screenattached
+
+#define GPIO_OUT (*((volatile unsigned char *) 0x20000000))
+
+unsigned int bootmessage[8][2] = {
+{0x00000000,0x00000000},          
+{0x7E3838FC,0x003CC63C},
+{0x5A6C6C66,0x0066E618},
+{0x18C6C666,0x00C0F618},
+{0x18C6C67C,0x00C0DE18}, 
+{0x18C6C666,0x00CECE18},
+{0x186C6C66,0x0066C618},
+{0x3C3838FC,0x003EC63C}
+};
+
+#endif
+
+int board_init (void)
+{
+	#ifdef screenattached
+
+	unsigned int i;
+  	unsigned char n;
+  	
+  	//create pointer to screen memory
+  	unsigned int *pScreen = (unsigned int *) 0x40000000;
+  	
+  	//clear screen memory
+  	for(i = 0; i < 2400; i++ ){
+  		*pScreen = 0;
+  		pScreen++;	
+  	}
+  	
+  	//set pointer back to start of screen memory
+  	pScreen = (unsigned int *) 0x40000000;
+  	
+  	//write booting message from array
+  	for(i = 0; i < 8; i++){
+  			for(n = 0; n < 2; n++){
+  				*pScreen = bootmessage[i][n];
+  				pScreen++;
+  			}
+  		pScreen = pScreen + 8;
+  	}
+	
+	//switch on backlight
+	GPIO_OUT |= 0x00000020;
+
+	#endif
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+#if CONFIG_NR_DRAM_BANKS == 2
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
+#endif
+	return 0;
+}
+
diff -Naur u-boot-1.1.3/board/actelm7/config.mk u-boot-actelm7/board/actelm7/config.mk
--- u-boot-1.1.3/board/actelm7/config.mk	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/board/actelm7/config.mk	2009-09-05 17:51:04.000000000 +0100
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x103EC3A0
+
+PLATFORM_CPPFLAGS += -Uarm
diff -Naur u-boot-1.1.3/board/actelm7/flash.c u-boot-actelm7/board/actelm7/flash.c
--- u-boot-1.1.3/board/actelm7/flash.c	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/board/actelm7/flash.c	2009-09-05 17:51:04.000000000 +0100
@@ -0,0 +1,286 @@
+/*
+ * Copyright (C) 2003 ETC s.r.o.
+ *
+ * This code was inspired by Marius Groeger and Kyle Harris code
+ * available in other board ports for U-Boot
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Written by Peter Figuli <peposh@etc.sk>, 2003.
+ *
+ */
+
+#include <common.h>
+#include "intel.h"
+
+
+/*
+ * This code should handle CFI FLASH memory device. This code is very
+ * minimalistic approach without many essential error handling code as well.
+ * Because U-Boot actually is missing smart handling of FLASH device,
+ * we just set flash_id to anything else to FLASH_UNKNOW, so common code
+ * can call us without any restrictions.
+ * TODO: Add CFI Query, to be able to determine FLASH device.
+ * TODO: Add error handling code
+ * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
+ *       hopefully may work with other configurations.
+ */
+
+//4 bytes long 32-bits
+#  define FLASH_BUS vu_long
+
+//two chips in parallell
+#    define FLASH_CMD( x ) (( x << 16 )| x )
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+static FLASH_BUS flash_status_reg (void)
+{
+
+	FLASH_BUS *addr = (FLASH_BUS *) 0;
+
+	*addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
+
+	return *addr;
+}
+
+static int flash_ready (ulong timeout)
+{
+	int ok = 1;
+	ulong temp = 0;
+
+	reset_timer_masked ();
+	while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
+		   FLASH_CMD (CFI_INTEL_SR_READY)) {
+		if (get_timer_masked () > timeout && timeout != 0) {
+			ok = 0;
+			break;
+		}
+	}
+	return ok;
+}
+
+
+ulong flash_init (void)
+{
+	int i;
+	unsigned long address = PHYS_FLASH_1;
+
+	flash_info[0].size = PHYS_FLASH_SIZE;
+	flash_info[0].sector_count = CFG_MAX_FLASH_SECT;
+	flash_info[0].flash_id = INTEL_MANUFACT;
+	memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT);
+
+	for (i = 0; i < CFG_MAX_FLASH_SECT; i++) {
+		flash_info[0].start[i] = address;
+
+		/* unlock each block after start. */
+		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
+		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
+		flash_ready (0);
+		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+
+		address += FLASH_SECT_SIZE;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+				   CFG_FLASH_BASE,
+				   CFG_FLASH_BASE + monitor_flash_len - 1,
+				   &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+				   CFG_ENV_ADDR,
+				   CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return PHYS_FLASH_SIZE;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	printf (" Intel vendor\n");
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if (!(i % 5)) {
+			printf ("\n");
+		}
+
+		printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, non_protected = 0, sector;
+	int rc = ERR_OK;
+
+	FLASH_BUS *address;
+
+	for (sector = s_first; sector <= s_last; sector++) {
+		if (!info->protect[sector]) {
+			non_protected++;
+		}
+	}
+
+	if (!non_protected) {
+		return ERR_PROTECTED;
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
+		if (info->protect[sector]) {
+			printf ("Protected sector %2d skipping...\n", sector);
+			continue;
+		} else {
+			printf ("Erasing sector %2d ... ", sector);
+		}
+
+		address = (FLASH_BUS *) (info->start[sector]);
+
+		*address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
+		*address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
+		if (flash_ready (CFG_FLASH_ERASE_TOUT)) {
+			*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
+			printf ("ok.\n");
+		} else {
+			*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
+			rc = ERR_TIMOUT;
+			printf ("timeout! Aborting...\n");
+			break;
+		}
+		*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+	}
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+	if (flag) {
+		enable_interrupts ();
+	}
+
+	return rc;
+}
+
+static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
+{
+	FLASH_BUS *address = (FLASH_BUS *) dest;
+	int rc = ERR_OK;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*address & data) != data) {
+		return ERR_NOT_ERASED;
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	flag = disable_interrupts ();
+
+	*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
+	*address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
+	*address = data;
+
+	if (!flash_ready (CFG_FLASH_WRITE_TOUT)) {
+		*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
+		rc = ERR_TIMOUT;
+		printf ("timeout! Aborting...\n");
+	}
+
+	*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+	if (flag) {
+		enable_interrupts ();
+	}
+
+	return rc;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong read_addr, write_addr;
+	FLASH_BUS data;
+	int i, result = ERR_OK;
+
+
+	read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
+	write_addr = read_addr;
+	if (read_addr != addr) {
+		data = 0;
+		for (i = 0; i < sizeof (FLASH_BUS); i++) {
+			if (read_addr < addr || cnt == 0) {
+				data |= *((uchar *) read_addr) << i * 8;
+			} else {
+				data |= (*src++) << i * 8;
+				cnt--;
+			}
+			read_addr++;
+		}
+		if ((result = write_data (info, write_addr, data)) != ERR_OK) {
+			return result;
+		}
+		write_addr += sizeof (FLASH_BUS);
+	}
+	for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
+		if ((result = write_data (info, write_addr,
+								  *((FLASH_BUS *) src))) != ERR_OK) {
+			return result;
+		}
+		write_addr += sizeof (FLASH_BUS);
+		src += sizeof (FLASH_BUS);
+	}
+	if (cnt > 0) {
+		read_addr = write_addr;
+		data = 0;
+		for (i = 0; i < sizeof (FLASH_BUS); i++) {
+			if (cnt > 0) {
+				data |= (*src++) << i * 8;
+				cnt--;
+			} else {
+				data |= *((uchar *) read_addr) << i * 8;
+			}
+			read_addr++;
+		}
+		if ((result = write_data (info, write_addr, data)) != 0) {
+			return result;
+		}
+	}
+	return ERR_OK;
+}
diff -Naur u-boot-1.1.3/board/actelm7/intel.h u-boot-actelm7/board/actelm7/intel.h
--- u-boot-1.1.3/board/actelm7/intel.h	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/board/actelm7/intel.h	2009-09-05 17:51:04.000000000 +0100
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2002 ETC s.r.o.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Written by Marcel Telka <marcel@telka.sk>, 2002.
+ *
+ * Documentation:
+ * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
+ *     28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
+ * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
+ *     28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
+ *
+ * This file is taken from OpenWinCE project hosted by SourceForge.net
+ *
+ */
+
+#ifndef	FLASH_INTEL_H
+#define	FLASH_INTEL_H
+
+#include <common.h>
+
+/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
+
+#define	CFI_INTEL_CMD_READ_ARRAY		0xFF	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_IDENTIFIER		0x90	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_QUERY		0x98	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_STATUS_REGISTER	0x70	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_CLEAR_STATUS_REGISTER	0x50	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_PROGRAM1			0x40	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_PROGRAM2			0x10	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_WRITE_TO_BUFFER		0xE8	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_CONFIRM			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_BLOCK_ERASE		0x20	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_SUSPEND			0xB0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_RESUME			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_SETUP		0x60	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_BLOCK		0x01	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_UNLOCK_BLOCK		0xD0	/* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_DOWN_BLOCK		0x2F	/* 28FxxxK3, 28FxxxK18 */
+
+/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
+
+#define	CFI_INTEL_SR_READY			1 << 7	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_ERASE_SUSPEND		1 << 6	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_ERASE_ERROR		1 << 5	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_PROGRAM_ERROR		1 << 4	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_VPEN_ERROR			1 << 3	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_PROGRAM_SUSPEND		1 << 2	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_BLOCK_LOCKED		1 << 1	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_BEFP			1 << 0	/* 28FxxxK3, 28FxxxK18 */
+
+/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
+
+#define	CFI_CHIP_INTEL_28F320J3A		0x0016
+#define	CFI_CHIPN_INTEL_28F320J3A		"28F320J3A"
+#define	CFI_CHIP_INTEL_28F640J3A		0x0017
+#define	CFI_CHIPN_INTEL_28F640J3A		"28F640J3A"
+#define	CFI_CHIP_INTEL_28F128J3A		0x0018
+#define	CFI_CHIPN_INTEL_28F128J3A		"28F128J3A"
+
+/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
+
+#define	CFI_CHIP_INTEL_28F640K3			0x8801
+#define	CFI_CHIPN_INTEL_28F640K3		"28F640K3"
+#define	CFI_CHIP_INTEL_28F128K3			0x8802
+#define	CFI_CHIPN_INTEL_28F128K3		"28F128K3"
+#define	CFI_CHIP_INTEL_28F256K3			0x8803
+#define	CFI_CHIPN_INTEL_28F256K3		"28F256K3"
+#define	CFI_CHIP_INTEL_28F640K18		0x8805
+#define	CFI_CHIPN_INTEL_28F640K18		"28F640K18"
+#define	CFI_CHIP_INTEL_28F128K18		0x8806
+#define	CFI_CHIPN_INTEL_28F128K18		"28F128K18"
+#define	CFI_CHIP_INTEL_28F256K18		0x8807
+#define	CFI_CHIPN_INTEL_28F256K18		"28F256K18"
+
+#endif /* FLASH_INTEL_H */
diff -Naur u-boot-1.1.3/board/actelm7/lowlevel_init.s u-boot-actelm7/board/actelm7/lowlevel_init.s
--- u-boot-1.1.3/board/actelm7/lowlevel_init.s	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/board/actelm7/lowlevel_init.s	2009-09-05 17:51:04.000000000 +0100
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ *
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * memsetup-sa1110.S (blob): memory setup for various SA1110 architectures
+ * Modified By MATTO
+ *
+ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+/*
+ * Documentation:
+ * Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
+ *     Advanced Developer's manual, December 1999
+ *
+ * Intel has a very hard to find SDRAM configurator on their web site:
+ *   http://appzone.intel.com/hcd/sa1110/memory/index.asp
+ *
+ * NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This
+ * appears to be true, but it might be possible that somebody designs a
+ * board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik
+ *
+ * 04-10-2001:  SELETZ
+ * - separated memory config for multiple platform support
+ * - perform SA1110 Hardware Reset Procedure
+ *
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+
+
+/* Nonething to do here no mam or sdram to setup */			
+  
+	mov pc, lr
+
diff -Naur u-boot-1.1.3/board/actelm7/Makefile u-boot-actelm7/board/actelm7/Makefile
--- u-boot-1.1.3/board/actelm7/Makefile	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/board/actelm7/Makefile	2009-09-05 17:51:04.000000000 +0100
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= actelm7.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff -Naur u-boot-1.1.3/board/actelm7/u-boot.lds u-boot-actelm7/board/actelm7/u-boot.lds
--- u-boot-1.1.3/board/actelm7/u-boot.lds	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/board/actelm7/u-boot.lds	2009-09-05 17:51:04.000000000 +0100
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm7tdmi/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+	armboot_end_data = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff -Naur u-boot-1.1.3/cpu/arm7tdmi/config.mk u-boot-actelm7/cpu/arm7tdmi/config.mk
--- u-boot-1.1.3/cpu/arm7tdmi/config.mk	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/cpu/arm7tdmi/config.mk	2009-09-05 17:51:04.000000000 +0100
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
+	-mshort-load-bytes -msoft-float
+
+PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi -msoft-float
diff -Naur u-boot-1.1.3/cpu/arm7tdmi/cpu.c u-boot-actelm7/cpu/arm7tdmi/cpu.c
--- u-boot-1.1.3/cpu/arm7tdmi/cpu.c	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/cpu/arm7tdmi/cpu.c	2009-09-05 17:51:04.000000000 +0100
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * S3C44B0 CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/hardware.h>
+
+
+
+
+int cpu_init (void)
+{
+	/*we have nothing to do here,cause we have no cache 
+	 *icache_enable();
+   */
+	return 0;
+}
+
+int cleanup_before_linux (void)
+{
+	/*
+		cache memory should be enabled before calling
+		Linux to make the kernel uncompression faster
+	*/
+	/*we have nothing to do here,cause we have no cache
+	 *icache_enable();
+   */
+	disable_interrupts ();
+
+	return 0;
+}
+
+void reset_cpu (ulong addr)
+{
+	/*
+		reset the cpu using watchdog
+	*/
+
+	 /* start the watchdog */
+  	WDOG_CONTROL = 0x00000010;
+	
+	/* set the timeout value to approx 2 seconds*/
+  	WDOG_LOAD = 0x00ff0000;
+  
+  /*wait ...*/
+	while(1) {
+		/*NOP*/
+	}
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	extern void reset_cpu (ulong addr);
+
+	disable_interrupts ();
+	reset_cpu (0);
+
+	/*NOTREACHED*/
+	return (0);
+}
+
+void icache_enable (void)
+{
+}
+
+void icache_disable (void)
+{
+}
+
+int icache_status (void)
+{
+	return 0;
+}
+
+void dcache_enable (void)
+{
+	icache_enable();
+}
+
+void dcache_disable (void)
+{
+	icache_disable();
+}
+
+int dcache_status (void)
+{
+	return icache_status();
+}
+
+/*
+	RTC stuff
+*/
+#include <rtc.h>
+#ifndef BCD2HEX
+	#define BCD2HEX(n)  ((n>>4)*10+(n&0x0f))
+#endif
+#ifndef HEX2BCD
+	#define HEX2BCD(x) ((((x) / 10) << 4) + (x) % 10)
+#endif
+
+void rtc_get (struct rtc_time* tm)
+{
+	
+}
+
+void rtc_set (struct rtc_time* tm)
+{
+	
+}
+
+void rtc_reset (void)
+{
+	
+}
+
+
diff -Naur u-boot-1.1.3/cpu/arm7tdmi/interrupts.c u-boot-actelm7/cpu/arm7tdmi/interrupts.c
--- u-boot-1.1.3/cpu/arm7tdmi/interrupts.c	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/cpu/arm7tdmi/interrupts.c	2009-09-05 17:51:04.000000000 +0100
@@ -0,0 +1,234 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+
+#include <asm/proc-armv/ptrace.h>
+
+extern void reset_cpu(ulong addr);
+
+/* we always count down the max. */
+#define TIMER_LOAD_VAL 0xffff
+
+/* macro to read the 16 bit timer */
+#define READ_TIMER (TIMER0_VALUE & 0x0000ffff)		//read timer0 reg mask off upper two bytes
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ NOT supported
+#else
+void enable_interrupts (void)
+{
+	return;
+}
+int disable_interrupts (void)
+{
+	return 0;
+}
+#endif
+
+
+void bad_mode (void)
+{
+	panic ("Resetting CPU ...\n");
+	reset_cpu (0);
+}
+
+void show_regs (struct pt_regs *regs)
+{
+	unsigned long flags;
+	const char *processor_modes[] =
+		{ "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
+				"UK6_26", "UK7_26",
+		"UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26",
+				"UK14_26", "UK15_26",
+		"USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32",
+				"UK6_32", "ABT_32",
+		"UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32",
+				"UK14_32", "SYS_32"
+	};
+
+	flags = condition_codes (regs);
+
+	printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
+			"sp : %08lx  ip : %08lx  fp : %08lx\n",
+			instruction_pointer (regs),
+			regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+	printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+			regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+	printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+			regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+	printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+			regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+	printf ("Flags: %c%c%c%c",
+			flags & CC_N_BIT ? 'N' : 'n',
+			flags & CC_Z_BIT ? 'Z' : 'z',
+			flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
+			interrupts_enabled (regs) ? "on" : "off",
+			fast_interrupts_enabled (regs) ? "on" : "off",
+			processor_modes[processor_mode (regs)],
+			thumb_mode (regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction (struct pt_regs *pt_regs)
+{
+	printf ("undefined instruction\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_software_interrupt (struct pt_regs *pt_regs)
+{
+	printf ("software interrupt\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_prefetch_abort (struct pt_regs *pt_regs)
+{
+	printf ("prefetch abort\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_data_abort (struct pt_regs *pt_regs)
+{
+	printf ("data abort\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_not_used (struct pt_regs *pt_regs)
+{
+	printf ("not used\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_fiq (struct pt_regs *pt_regs)
+{
+	printf ("fast interrupt request\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_irq (struct pt_regs *pt_regs)
+{
+	printf ("interrupt request\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+int interrupt_init (void)
+{
+	TIMER0_PRESCALE = 0x00000009;		//Setup timer0 prescaler to divide by 1024
+	TIMER0_LOAD = 0x0000ffff;			//timer is loaded with this value when it get
+										//to zero
+	TIMER0_CONTROL = 0x00000001;		//enable timer0, interrupts off, continous mode 
+
+	lastdec = TIMER_LOAD_VAL;			//load lastdec value with 0x0000ffff
+	timestamp = 0;						//clear time stamp variable
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+void udelay (unsigned long usec)	//if 1000us (1ms) was passed to this function
+{
+	ulong tmo;					
+
+	tmo = usec / 1000;			//tmo would now hold 1 
+	tmo *= CFG_HZ;				//cfg_hz = 10000 so tmo = 10000
+	tmo /= 1000;				//tmo now holds = 10
+
+	tmo += get_timer (0);		//get current timestamp and add to tmo
+
+	while (get_timer_masked () < tmo)  //stay here until timer reaches the value in tmo
+	/*NOP*/;						   //10 * (1/10000hz) = 1000us (1ms)
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastdec = READ_TIMER;			//update lastdec value with current value of timer0
+	timestamp = 0;					//clear timestamp
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER;			//read current value of timer0
+
+	if (now <= lastdec) {			//is the time now greater then last time this function
+		timestamp += lastdec - now; //was called (this is normally the case).If is update
+									//timestamp by adding the differnce between last call
+									//time and the time now to timestamp.
+	} else {
+									// we have an overflow (taken to long to call function)
+		timestamp += (TIMER_LOAD_VAL - now) + lastdec; //take the roll over into account when
+									//working out the new time stamp value
+
+	}
+	lastdec = now;					//update lastdec value with current value of timer0
+
+	return timestamp;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong tmo;
+
+	tmo = usec / 1000;
+	tmo *= CFG_HZ;
+	tmo /= 1000;
+
+	tmo += get_timer (0);
+
+	reset_timer_masked ();				//reset timestamp & update lastdec value
+
+	while (get_timer_masked () < tmo)
+		/*NOP*/;
+}
diff -Naur u-boot-1.1.3/cpu/arm7tdmi/Makefile u-boot-actelm7/cpu/arm7tdmi/Makefile
--- u-boot-1.1.3/cpu/arm7tdmi/Makefile	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/cpu/arm7tdmi/Makefile	2009-09-05 17:51:04.000000000 +0100
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(CPU).a
+
+START	= start.o
+OBJS	= serial.o interrupts.o cpu.o
+
+all:	.depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff -Naur u-boot-1.1.3/cpu/arm7tdmi/serial.c u-boot-actelm7/cpu/arm7tdmi/serial.c
--- u-boot-1.1.3/cpu/arm7tdmi/serial.c	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/cpu/arm7tdmi/serial.c	2009-09-09 21:10:25.000000000 +0100
@@ -0,0 +1,197 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+
+#define	USRRxData      	(1 << 0)
+#define	USRTxHoldEmpty 	(1 << 5)
+#define GET_CHAR(p)	p
+#define PUT_CHAR(p,c)  	(p= (unsigned )(c))
+#define TX_READY(s)    	((s) & USRTxHoldEmpty)
+#define RX_DATA(s)     	((s) & USRRxData)
+
+/* flush serial input queue. returns 0 on success or negative error
+ * number otherwise
+ */
+static int serial_flush_input(void)
+{
+	volatile u32 tmp;
+
+	/* keep on reading as long as the receiver is not empty */
+	while(RX_DATA(UART0_LSR)) {
+		tmp = GET_CHAR(UART0_REC_REG);
+	}
+
+	return 0;
+}
+
+
+/* flush output queue. returns 0 on success or negative error number
+ * otherwise
+ */
+static int serial_flush_output(void)
+{
+	/* wait until the transmitter is no longer busy */
+	while(TX_READY(UART0_LSR)==0) {
+	}
+
+	return 0;
+}
+
+
+void serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	u32 divisor = 0;
+
+	/* get correct divisor */
+	switch(gd->baudrate) {
+
+	case 1200:
+    divisor = 1042; 
+		break;
+
+	case 9600:
+    divisor = 130;
+		break;
+
+	case 19200:
+    divisor = 65;
+		break;
+
+	case 38400:
+    divisor = 33;
+		break;
+
+	case 57600:
+    divisor = 22;
+		break;
+
+	case 115200:
+    divisor = 11;
+
+	}
+
+	UART0_LCR = 0x83;			//enable latches, 8 bit word, no parity
+
+	if(divisor==1042)
+		{
+			UART0_DLR = 0x12;	
+			UART0_DMR = 0x04;	
+			}
+	else
+		{
+			UART0_DLR = divisor;
+			UART0_DMR = 0x00;
+		}
+
+	UART0_LCR = 0x03;			//disable latches data 8 bits, 1 stop bit, No parity
+	
+	serial_flush_output();				//make sure tx is empty
+	serial_flush_input();				//make sure rx is empty
+	
+	for(divisor=0; divisor<100; divisor++) {
+		/* NOP */
+	}
+}
+
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int serial_init (void)
+{
+	serial_setbrg ();
+
+	return (0);
+}
+
+
+/*
+ * Output a single byte to the serial port.
+ */
+void serial_putc (const char c)
+{
+	/* wait for room in the transmit FIFO */
+	while(TX_READY(UART0_LSR)==0);
+
+	PUT_CHAR(UART0_TRANS_REG,c);
+
+	/*
+		to be polite with serial console add a line feed
+		to the carriage return character
+	*/
+	if (c=='\n')
+		serial_putc('\r');
+}
+
+/*
+ * check to see if there is any data in rx reg returns 1 if there is
+ * otherwise return 0.
+ */
+int serial_tstc (void)
+{
+	return (RX_DATA(UART0_LSR));
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_getc (void)
+{
+	int rv;
+
+	for(;;) {
+		rv = serial_tstc();
+
+		if(rv > 0)
+			return (GET_CHAR(UART0_REC_REG));
+	}
+}
+
+void
+serial_puts (const char *s)
+{
+	while (*s != 0) {
+		serial_putc (*s++);
+	}
+}
diff -Naur u-boot-1.1.3/cpu/arm7tdmi/start.S u-boot-actelm7/cpu/arm7tdmi/start.S
--- u-boot-1.1.3/cpu/arm7tdmi/start.S	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/cpu/arm7tdmi/start.S	2009-09-05 17:51:04.000000000 +0100
@@ -0,0 +1,216 @@
+/*
+ * Startup Code for lpc2294 CPU-core
+ *
+ * (C) Copyright 2005
+ * jay
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/*
+ * Jump vector table
+ */
+
+
+.globl _start
+_start: 
+	b	reset
+        ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:
+	.word 0x10000004
+_software_interrupt:
+	.word 0x10000008
+_prefetch_abort:
+	.word 0x1000000c
+_data_abort:
+	.word 0x10000010
+_not_used:
+	.word 0
+_irq:
+	.word 0x10000018
+_fiq:
+	.word 0x1000001c
+
+/*_undefined_instruction:
+	.word undefined_instruction
+_software_interrupt:
+	.word software_interrupt
+_prefetch_abort:
+	.word prefetch_abort
+_data_abort:
+	.word data_abort
+_not_used:
+	.word not_used
+_irq:
+	.word irq
+_fiq:
+	.word fiq */
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * relocate u-boot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+	.word _start
+
+/*
+ * These are defined in the board-specific linker script.
+ */
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode,disable all interrupts
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x3f
+	orr	r0,r0,#0x13
+	orr r0,r0,#0x80
+	orr r0,r0,#0x40
+	msr	cpsr,r0
+
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */
+				
+
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
+relocate:				/* relocate U-Boot to RAM	    */
+	adr	r0, _start		/* r0 <- current position of code   */
+	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
+	cmp     r0, r1                  /* don't reloc during debug         */
+	beq     stack_setup
+
+	ldr	r2, _armboot_start
+	ldr	r3, _bss_start
+	sub	r2, r3, r2		/* r2 <- size of armboot            */
+	add	r2, r0, r2		/* r2 <- source end address         */
+
+copy_loop:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end addreee [r2]    */
+	ble	copy_loop
+
+#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
+
+	/* Set up the stack */
+stack_setup:
+	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
+	sub	r0, r0, #CFG_MALLOC_LEN	/* malloc area                      */
+	sub	r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
+#ifdef CONFIG_USE_IRQ
+	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
+#endif
+	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
+
+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000		/* clear                            */
+
+clbss_l:str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	ble	clbss_l
+
+	ldr	pc, _start_armboot
+
+_start_armboot:	.word start_armboot
+
+/*
+ * exception handlers
+ */
+
+/*undefined_instruction:
+	mov	r6, #3
+	b	reset
+
+software_interrupt:
+	mov	r6, #4
+	b	reset
+
+prefetch_abort:
+	mov	r6, #5
+	b	reset
+
+data_abort:
+	mov	r6, #6
+	b	reset
+
+not_used:
+	mov	r6, #7
+	b	reset
+
+irq:
+	mov	r6, #8
+	b	reset
+
+fiq:
+	mov	r6, #9
+	b	reset  */
diff -Naur u-boot-1.1.3/drivers/rtl8019.c u-boot-actelm7/drivers/rtl8019.c
--- u-boot-1.1.3/drivers/rtl8019.c	2005-08-14 00:53:35.000000000 +0100
+++ u-boot-actelm7/drivers/rtl8019.c	2009-09-05 17:51:04.000000000 +0100
@@ -99,6 +99,15 @@
 
 int eth_init (bd_t * bd)
 {
+	
+#ifdef CONFIG_LPC
+	put_reg (RTL8019_COMMAND, RTL8019_PAGE3);
+	put_reg (RTL8019_CR9346, 0xcf);
+	put_reg (RTL8019_CONFIG3, 0x60);
+	put_reg (RTL8019_CR9346, 0x0f);
+	put_reg (RTL8019_COMMAND, RTL8019_PAGE0);
+#endif
+	
 	eth_reset ();
 	put_reg (RTL8019_COMMAND, RTL8019_PAGE0STOP);
 	put_reg (RTL8019_DATACONFIGURATION, 0x48);
diff -Naur u-boot-1.1.3/drivers/rtl8019.h u-boot-actelm7/drivers/rtl8019.h
--- u-boot-1.1.3/drivers/rtl8019.h	2005-08-14 00:53:35.000000000 +0100
+++ u-boot-actelm7/drivers/rtl8019.h	2009-09-05 17:51:04.000000000 +0100
@@ -33,6 +33,39 @@
 
 #ifdef CONFIG_DRIVER_RTL8019
 
+#ifdef CONFIG_LPC
+
+#define   ETH_ADDR_SFT              (1)
+#define   EI_SHIFT(x)               ((x)<<ETH_ADDR_SFT)
+#define   RTL8019_REG_00            (RTL8019_BASE + EI_SHIFT(0x00))
+#define 	RTL8019_REG_01        		(RTL8019_BASE + EI_SHIFT(0x01)) 
+#define 	RTL8019_REG_02        		(RTL8019_BASE + EI_SHIFT(0x02))
+#define 	RTL8019_REG_03        		(RTL8019_BASE + EI_SHIFT(0x03))
+#define 	RTL8019_REG_04        		(RTL8019_BASE + EI_SHIFT(0x04))
+#define 	RTL8019_REG_05        		(RTL8019_BASE + EI_SHIFT(0x05))
+#define 	RTL8019_REG_06        		(RTL8019_BASE + EI_SHIFT(0x06))
+#define 	RTL8019_REG_07        		(RTL8019_BASE + EI_SHIFT(0x07))
+#define 	RTL8019_REG_08        		(RTL8019_BASE + EI_SHIFT(0x08))
+#define 	RTL8019_REG_09        		(RTL8019_BASE + EI_SHIFT(0x09))
+#define 	RTL8019_REG_0a        		(RTL8019_BASE + EI_SHIFT(0x0a))
+#define 	RTL8019_REG_0b        		(RTL8019_BASE + EI_SHIFT(0x0b))
+#define 	RTL8019_REG_0c        		(RTL8019_BASE + EI_SHIFT(0x0c))
+#define 	RTL8019_REG_0d        		(RTL8019_BASE + EI_SHIFT(0x0d))
+#define 	RTL8019_REG_0e       	 	  (RTL8019_BASE + EI_SHIFT(0x0e))
+#define 	RTL8019_REG_0f        		(RTL8019_BASE + EI_SHIFT(0x0f))
+#define 	RTL8019_REG_10        		(RTL8019_BASE + EI_SHIFT(0x10))
+#define 	RTL8019_REG_1f        		(RTL8019_BASE + EI_SHIFT(0x1f))
+
+#define   RTL8019_CR9346    RTL8019_REG_01
+#define   RTL8019_CONFIG0   RTL8019_REG_03
+#define   RTL8019_CONFIG1   RTL8019_REG_04
+#define   RTL8019_CONFIG2   RTL8019_REG_05
+#define   RTL8019_CONFIG3   RTL8019_REG_06
+
+#define   RTL8019_PAGE3                   0xE2
+
+#else
+
 #define		RTL8019_REG_00        		(RTL8019_BASE + 0x00)
 #define 	RTL8019_REG_01        		(RTL8019_BASE + 0x01)
 #define 	RTL8019_REG_02        		(RTL8019_BASE + 0x02)
@@ -52,6 +85,8 @@
 #define 	RTL8019_REG_10        		(RTL8019_BASE + 0x10)
 #define 	RTL8019_REG_1f        		(RTL8019_BASE + 0x1f)
 
+#endif
+
 #define		RTL8019_COMMAND			RTL8019_REG_00
 #define		RTL8019_PAGESTART		RTL8019_REG_01
 #define		RTL8019_PAGESTOP		RTL8019_REG_02
diff -Naur u-boot-1.1.3/examples/Makefile u-boot-actelm7/examples/Makefile
--- u-boot-1.1.3/examples/Makefile	2005-08-14 00:53:35.000000000 +0100
+++ u-boot-actelm7/examples/Makefile	2009-09-05 17:51:04.000000000 +0100
@@ -55,8 +55,8 @@
 
 include $(TOPDIR)/config.mk
 
-SREC	= hello_world.srec
-BIN	= hello_world.bin hello_world
+#SREC	= hello_world.srec
+#BIN	= hello_world.bin hello_world
 
 ifeq ($(CPU),mpc8xx)
 SREC	= test_burst.srec
diff -Naur u-boot-1.1.3/include/asm-arm/arch-arm7tdmi/hardware.h u-boot-actelm7/include/asm-arm/arch-arm7tdmi/hardware.h
--- u-boot-1.1.3/include/asm-arm/arch-arm7tdmi/hardware.h	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/include/asm-arm/arch-arm7tdmi/hardware.h	2009-09-05 17:51:04.000000000 +0100
@@ -0,0 +1,36 @@
+/********************************************************/
+/*							*/
+/* 					*/
+/* 					*/
+/*							*/
+/********************************************************/
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/* Timer 0 */
+
+#define TIMER0_LOAD       (*((volatile unsigned long *) 0x21000000))
+#define TIMER0_VALUE      (*((volatile unsigned long *) 0x21000004))
+#define TIMER0_CONTROL    (*((volatile unsigned long *) 0x21000008))
+#define TIMER0_PRESCALE   (*((volatile unsigned long *) 0x2100000C))
+#define TIMER0_INT_CONT   (*((volatile unsigned long *) 0x21000010))
+#define TIMER0_RIS        (*((volatile unsigned long *) 0x21000014))
+#define TIMER0_MIS        (*((volatile unsigned long *) 0x21000018))
+
+/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
+
+#define UART0_TRANS_REG          (*((volatile unsigned char *) 0x22000000))
+#define UART0_REC_REG            (*((volatile unsigned char *) 0x22000000))
+#define UART0_DLR		 (*((volatile unsigned char *) 0x22000000))
+#define UART0_DMR		 (*((volatile unsigned char *) 0x22000004))
+#define UART0_LCR		 (*((volatile unsigned char *) 0x2200000C))
+#define UART0_LSR		 (*((volatile unsigned char *) 0x22000014))
+
+/* Watchdog */
+
+#define WDOG_LOAD           (*((volatile unsigned long *) 0x23000000))
+#define WDOG_VALUE          (*((volatile unsigned long *) 0x23000004))
+#define WDOG_CONTROL        (*((volatile unsigned long *) 0x23000008))
+#define WDOG_REFRESH        (*((volatile unsigned long *) 0x2300000C))
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff -Naur u-boot-1.1.3/include/configs/actelm7.h u-boot-actelm7/include/configs/actelm7.h
--- u-boot-1.1.3/include/configs/actelm7.h	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-actelm7/include/configs/actelm7.h	2009-09-09 20:54:13.000000000 +0100
@@ -0,0 +1,169 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ *
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * Configuation settings for the lpc board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7			1	/* This is a ARM7 CPU	*/
+#define CONFIG_ARM_THUMB	1	/* this is an ARM7TDMI  */
+#undef  CONFIG_ARM7_REVD	 	/* disable ARM720 REV.D Workarounds */
+
+#undef CONFIG_USE_IRQ			/* don't need them anymore */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MONITOR_LEN		(74 * 1024)	/* Reserve 74 kB for Monitor	*/
+#define CFG_ENV_SIZE		1024			/* 1024 bytes may be used for env vars*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024 )
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_MONITOR_BASE	0x00000000 /*base of flash */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		1	/* we use Serial line 1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_COMMANDS		((CONFIG_CMD_DFL & ~CFG_CMD_NET)  | \
+								CFG_CMD_ELF | \
+								CFG_CMD_FLASH | \
+								CFG_CMD_ENV)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTARGS  "console=ttyS0,115200n8"
+#define CONFIG_BOOTFILE	 "linux.bin"
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTCOMMAND "go 80000"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"=>  "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x10008000	/* default load address	*/
+
+#define	CFG_HZ				(20000000 / 1024)  // pclk set to 20mhz however timer0 prescale set to 1024
+							   // therefore one tick of timer0 is 19531hz
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_MEMTEST_START   0x10000000	/* memtest works on		*/
+#define CFG_MEMTEST_END	    0x10396000	/* 0 ... 3.6 MB in SRAM		*/
+#define screenattached	1		/* board has a qvga screen attached */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks of SRAM */
+#define PHYS_SDRAM_1		0x10000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x00400000 /* 4 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE		0x00800000 /* 8 MB */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	32	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	(60 * CFG_HZ)	/* Timeout for Flash Erase (max ticks before time out)	*/
+#define CFG_FLASH_WRITE_TOUT	CFG_HZ	/* Timeout for Flash Write (max ticks before time out)	*/
+
+#define FLASH_SECT_SIZE	    0x00040000	/* size of erase sector	*/
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#undef CFG_ENV_IS_NOWHERE
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) /* environment start address */
+#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ 
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (STM24C02W6) for environment
+ */
+
+
+/* Flash banks JFFS2 should use */
+/*
+#define CFG_JFFS2_FIRST_BANK    0
+#define CFG_JFFS2_FIRST_SECTOR	2
+#define CFG_JFFS2_NUM_BANKS     1
+*/
+
+/*
+	Linux TAGs (see lib_arm/armlinux.c)
+*/
+#define CONFIG_CMDLINE_TAG
+#undef CONFIG_SETUP_MEMORY_TAGS
+/*#define CONFIG_INITRD_TAG */
+
+#endif	/* __CONFIG_H */
diff -Naur u-boot-1.1.3/Makefile u-boot-actelm7/Makefile
--- u-boot-1.1.3/Makefile	2005-08-14 00:53:35.000000000 +0100
+++ u-boot-actelm7/Makefile	2009-09-05 17:51:04.000000000 +0100
@@ -57,7 +57,7 @@
 CROSS_COMPILE = powerpc-linux-
 endif
 ifeq ($(ARCH),arm)
-CROSS_COMPILE = arm-linux-
+CROSS_COMPILE = arm-elf-
 endif
 ifeq ($(ARCH),i386)
 ifeq ($(HOSTARCH),i386)
@@ -1490,6 +1490,13 @@
 	@./mkconfig $(@:_config=) arm s3c44b0 B2 dave
 
 #########################################################################
+## LPC2294 Systems
+#########################################################################
+
+actelm7_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm7tdmi actelm7
+
+#########################################################################
 ## ARM720T Systems
 #########################################################################
 
