toplevel_p2xh Project Status (08/31/2015 - 23:14:20)
Project File: gcdv_update.xise Parser Errors: No Errors
Module Name: toplevel_p2xh Implementation State: Programming File Generated
Target Device: xc3s50a-4vq100
  • Errors:
No Errors
Product Version:ISE 14.4
  • Warnings:
99 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 1,024 1,408 72%  
Number of 4 input LUTs 1,246 1,408 88%  
Number of occupied Slices 704 704 100%  
    Number of Slices containing only related logic 704 704 100%  
    Number of Slices containing unrelated logic 0 704 0%  
Total Number of 4 input LUTs 1,315 1,408 93%  
    Number used as logic 1,163      
    Number used as a route-thru 69      
    Number used as Shift registers 83      
Number of bonded IOBs 23 68 33%  
    IOB Flip Flops 9      
    IOB Master Pads 4      
    IOB Slave Pads 4      
Number of ODDR2s used 4      
Number of BUFGMUXs 4 24 16%  
Number of DCMs 2 2 100%  
Number of MULT18X18SIOs 3 3 100%  
Number of RAMB16BWEs 2 3 66%  
Average Fanout of Non-Clock Nets 3.28      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon 31. Aug 23:12:20 2015061 Warnings (0 new)40 Infos (0 new)
Translation ReportCurrentMon 31. Aug 23:12:35 2015006 Infos (0 new)
Map ReportCurrentMon 31. Aug 23:13:31 2015019 Warnings (0 new)7 Infos (0 new)
Place and Route ReportCurrentMon 31. Aug 23:13:49 2015000
Power Report     
Post-PAR Static Timing ReportCurrentMon 31. Aug 23:13:56 2015005 Infos (0 new)
Bitgen ReportCurrentMon 31. Aug 23:14:09 2015019 Warnings (0 new)2 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
Physical Synthesis ReportCurrentMon 31. Aug 23:13:31 2015
WebTalk ReportCurrentMon 31. Aug 23:14:11 2015
WebTalk Log FileCurrentMon 31. Aug 23:14:20 2015

Date Generated: 08/31/2015 - 23:14:20