toplevel_p2xh Project Status (08/25/2015 - 21:35:19) | |||
Project File: | gcdv_update.xise | Parser Errors: | No Errors |
Module Name: | toplevel_p2xh | Implementation State: | Programming File Generated |
Target Device: | xc3s50a-4vq100 |
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No Errors |
Product Version: | ISE 14.4 |
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89 Warnings (1 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 951 | 1,408 | 67% | ||
Number of 4 input LUTs | 1,118 | 1,408 | 79% | ||
Number of occupied Slices | 702 | 704 | 99% | ||
Number of Slices containing only related logic | 702 | 702 | 100% | ||
Number of Slices containing unrelated logic | 0 | 702 | 0% | ||
Total Number of 4 input LUTs | 1,198 | 1,408 | 85% | ||
Number used as logic | 1,051 | ||||
Number used as a route-thru | 80 | ||||
Number used as Shift registers | 67 | ||||
Number of bonded IOBs | 22 | 68 | 32% | ||
IOB Master Pads | 4 | ||||
IOB Slave Pads | 4 | ||||
Number of ODDR2s used | 4 | ||||
Number of BUFGMUXs | 4 | 24 | 16% | ||
Number of DCMs | 2 | 2 | 100% | ||
Number of MULT18X18SIOs | 3 | 3 | 100% | ||
Number of RAMB16BWEs | 2 | 3 | 66% | ||
Average Fanout of Non-Clock Nets | 3.22 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Tue 25. Aug 21:34:09 2015 | 0 | 51 Warnings (1 new) | 37 Infos (0 new) | |
Translation Report | Current | Tue 25. Aug 21:34:20 2015 | 0 | 0 | 6 Infos (0 new) | |
Map Report | Current | Tue 25. Aug 21:34:28 2015 | 0 | 19 Warnings (0 new) | 4 Infos (0 new) | |
Place and Route Report | Current | Tue 25. Aug 21:34:53 2015 | 0 | 0 | 0 | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Tue 25. Aug 21:35:00 2015 | 0 | 0 | 5 Infos (0 new) | |
Bitgen Report | Current | Tue 25. Aug 21:35:11 2015 | 0 | 19 Warnings (0 new) | 2 Infos (0 new) |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | Tue 25. Aug 21:35:12 2015 | |
WebTalk Log File | Current | Tue 25. Aug 21:35:19 2015 |