Timing Report

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Design Name usbexi
Device, Speed (SpeedFile Version) XC2C256, -7 (14.0 Advance Product Specification)
Date Created Mon Dec 23 00:03:04 2013
Created By Timing Report Generator: version P.49d
Copyright Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 6.600 ns.
Max. Clock Frequency (fSYSTEM) 151.515 MHz.
Limited by Cycle Time for exi_clk
Clock to Setup (tCYC) 6.600 ns.
Clock Pad to Output Pad Delay (tCO) 6.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 6.6 11 11
AUTO_TS_P2P 0.0 6.0 1 1
AUTO_TS_P2F 0.0 2.7 1 1
AUTO_TS_F2P 0.0 3.3 1 1


Constraint: TS1000

Description: PERIOD:PERIOD_exi_clk:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
exi_count<0>.Q to exi_count<1>.D 0.000 6.600 -6.600
exi_count<0>.Q to exi_count<2>.D 0.000 6.600 -6.600
exi_count<0>.Q to exi_count<3>.D 0.000 6.600 -6.600


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
exi_clk to exi_do 0.000 6.000 -6.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
exi_clk to exi_clk.GCK 0.000 2.700 -2.700


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
exi_do.Q to exi_do 0.000 3.300 -3.300



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
exi_clk 151.515 Limited by Cycle Time for exi_clk

Setup/Hold Times for Clocks


Clock to Pad Timing

Clock exi_clk to Pad
Destination Pad Clock (edge) to Pad
exi_do 6.000


Clock to Setup Times for Clocks

Clock to Setup for clock exi_clk
Source Destination Delay
exi_count<0>.Q exi_count<1>.D 6.600
exi_count<0>.Q exi_count<2>.D 6.600
exi_count<0>.Q exi_count<3>.D 6.600
exi_count<0>.Q exi_do.D 6.600
exi_count<1>.Q exi_count<2>.D 6.600
exi_count<1>.Q exi_count<3>.D 6.600
exi_count<1>.Q exi_do.D 6.600
exi_count<2>.Q exi_count<3>.D 6.600
exi_count<2>.Q exi_do.D 6.600
exi_count<3>.Q exi_do.D 6.600
exi_do.Q exi_do.D 6.600


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 14
Number of Timing errors: 14
Analysis Completed: Mon Dec 23 00:03:04 2013